The Silicon Vertex Detector (SVD) design consists of four layers of double sided silicon strip sensors fabricated from six-inches silicon wafers. The sensors are used to assemble slices of every layer, called “ladders”, which are then organised in a barrel geometry, with slanted sensors in the forward region to maximise the angular acceptance. The final SVD layout is shown in the drawing of fig.1.

The SVD, together with the PXD and the CDC, will allow the reconstruction of the trajectories of charged particles produced in the decay of B mesons. Moreover, when charged particles pass through matter, they lose energy inside the material. With the SVD will be possible to estimate the amount of energy loss for particles passing through sensors, and with this information the identification of the particles will be done.

One of the main features of the SVD is the so called “Origami concept”. While the layer 3 ladders consist of just 2 sensors, for which the read-out electronics is placed outside the active volume, the ladders of layers 4, 5 and 6 have inner sensors, like the ones in fig.2, that shows the structure of a layer 6 ladder. For these sensors, the read-out electronics must be placed inside the active volume of the SVD. This means that, since the SVD is very close to the interaction point between the two beams and will be subject to a lot of radiation, the electronics must be able to receive a very high radiation dose without degrading its performance. The APV25 chip was chosen to read-out the sensors, because is very fast (its shaping time is of the order of 50 nanoseconds) and can get a radiation dose higher than the one expected in the SVD active region. The Origami is a three-layer kapton flexible circuit (shown in fig. 2) conceived to position read-out chips on top of each inner sensor, all on the same side and on the same line, so that just one cooling channel is required, keeping low the average material budget of every ladder, which is essential to preserve the precision in the vertex reconstruction. The Origami flex circuits are used also to bring data stored in the read-out chips to the Data Acquisition system. This concept adds lots of challenges in the ladder assembly procedures, but it’s necessary to ensure the best performance to the Silicon Vertex Detector.

Another important feature of the SVD comes from the need of reducing the huge amount of data coming from the PXD, that are difficult to read-out in a short time. SVD data can be used to track in real time charged particles trajectories in order to define the region in which a particle should have hit the PXD. In this way just the small fraction of PXD data coming from that region is read-out. These regions are called ROI, “Regions Of Interest”, and are another challenge for the whole Silicon Vertex Detector.

The SVD working group includes several institutions all around the World (Australia, Austria, India, Italy, Japan) that are sharing the efforts in order to assemble and install such a complex and fascinating detector.

Below other characteristics of the BelleII SVD:

• 3 different types of sensors: small rectangular (used for Layer 3), large rectangular, wedge sensors (for the slanted parts).
• 162 sensors used, 324 flat cables coming out from the SVD.
• pitch on phi-side: between 50 and 75 um
• pitch on z-side: between 160 and 240 um
• total silicon area: ~1.21 m^2
• 1748 readout chips, for a total of 223744 readout channels.
• power consumption: 2.31 mW/channel, 517 W for the whole SVD.
• inner radius (Layer 3): 39 mm
• outer radius (Layer 6): 140 mm
• angular acceptance: 17˚
• average material budget: x = 0.6% X0